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dbis
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Publications
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2025
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To stride or not to stride the memory access?
Reviews (DIMES 2025)
should be on the DRAM side, e.g., bank-level parallelism (BLP) vs row buffer locality. Note that DDR5 essentially doubled the amount of bank-level parallelism (due to subchannels) iso channel count. And [...] times and still was confused by exactly what you mean, e.g., the effects from TLB. For example, Fig. 5 lacks any note of which architecture it ran on, unlike Fig. 4. Please add architecture, memory placement …